Title: Improved Arithmetic and FPGA Implement of Motion Estimation
Abstract: In this paper, a new algorithm and its efficient hardware architecture for motion estimation based on a fullsearch block-matching algorithm is proposed for the low bit rate video coding H 263 and MPEG4 SP etc This architecture presents full utilization of the hardware resources, parallel processing architecture and repetitive data technique As a result, the computational time is saved For a CIF image and the searching range of motion vector -16~+15 5,the experience show that the speed for encoding can reach 25 f/s
Publication Year: 2004
Publication Date: 2004-01-01
Language: en
Type: article
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