Title: An Alterable Parameter Viterbi Decoder Hardware Solution
Abstract: A novel alterable parameter Viterbi decoder is presented,which supports constraint lengths from 3 to 7 and code rates 1/2 and 1/3.This decoder is synthesized on an FPGA.The results show that the overhead hardware resource associated with such a reconfigurable implementation as compared to a fixed constraint length 7 is no more than 8%,with a throughput of 20 Mbps.
Publication Year: 2005
Publication Date: 2005-01-01
Language: en
Type: article
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