Title: Synchroscalar: a low-power tile-based media architecture
Abstract: A fundamental shift from workstation computing to embedded and mobile computing has brought new challenges. Whereas previous generations of computing devices were concerned with maximizing performance and were contained within workstations, modern computing devices often low-power, embedded or mobile consumer products. This shift in computing has brought new challenges to the design of computer architectures. Three of these challenges are: building low-power flexible architectures for embedding computing, managing the environmental impact of these computer architectures, and ensuring the reliability of these computer architectures.
Previous generations of low-power devices have had to rely on fixed-function architectures which sacrifice programmability to achieve low-power operation. However, programmability is important because of increasing non-recurring engineering costs that are part of any new design. To address the issues of flexible, low-power processing, the Synchroscalar architecture was developed. Synchroscalar borrows ASIC techniques like parallelism and custom voltage and frequency domains to reduce operating power. The results are power efficiencies within 8-30X of known ASIC implementations, which is 10-60X better than conventional processors.
Because of the commoditization of computing, we must also be mindful of the impact these computing devices have on the environment. Due to the high amount of energy required to manufacture a processor, we propose that processors should be re-used from one device to the next in order to minimize their lifetime energy consumption. This document details a framework by which to evaluate processor for re-use, and quantifies those benefits.
Finally, as the technology we use to manufacture processors employs finer transistor geometries, we find that the reliability these embedded processors also decrease. This dissertation develops a method for measuring and monitoring the reliability of a processor, and then managing that reliability to ensure an expected lifetime of the processor.
Publication Year: 2007
Publication Date: 2007-01-01
Language: en
Type: article
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