Title: Improvement of Power and Performance in NAND and D-Latch Gates Using CNFET Technology
Abstract: In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice . Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.
Publication Year: 2015
Publication Date: 2015-06-01
Language: en
Type: article
Indexed In: ['crossref']
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