Title: Design of a Novel Optimized MAC Unit using Modified Fault Tolerant Vedic Multiplier
Abstract: In this study, the design of optimized Multiplication and Accumulation (MAC) unit with modified Vedic multiplier is presented. To design a MAC unit, efficient multiplier is used to increase speed and to reduce area and power. Conventional MAC is designed using without fault tolerant Vedic multiplier. But it consumes more area and power. And also less delay. So MAC unit is changed to design the efficient Vedic multiplier. Conventional MAC unit with regular Vedic multiplier is not working for some of the inputs condition. To overcome this fault, novel Vedic multiplier is proposed and designed using less half adder and Full Adder. Simulation is carried out using Modelsim 6.3c. Synthesis and Implementation is carried out using Xilinx and FPGA Spartan 3.