Title: A VLSI architecture for adaptive signal processing
Abstract: A VLSI architecture for direct parallel implementation of N-tap LMS (least mean square) adaptive filters is presented which uses N multiplier-accumulators and N-1 parallel adders. It will take two multiply delays and log/sub 2/ N add delays for each sampled datum. A prototype VLSI processor which can implement 16-tap adaptive filters on a single chip was also developed. The processor has very good architectural features, such as modularity, regularity, and cascadability. By cascading the processors, a very-high-order adaptive filter can be implemented in real time with a several-megahertz sampling rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Publication Year: 2002
Publication Date: 2002-12-09
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 3
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