Title: Systolic array implementation of multipliers for finite fields GF(2/sup m/)
Abstract: A parallel-in-parallel-out systolic array and a serial-in-serial-out systolic array are proposed for fast multiplication in finite fields GF(2/sup m/) with the standard basis representation. Both of the architectures possess features of regularity, modularity, concurrency, and unidirectional data flow. As a consequence, they have high throughput rates and are well suited to VLSI implementation with fault-tolerant design. As compared to the related multipliers presented by C.S. Yeh et al. (see IEEE Trans. Comput., vol.C-33, p.357-360, Apr. 1984), the proposed parallel implementation makes it easier to incorporate fault-tolerant design, and the proposed serial implementation requires only one control signal instead of two.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Publication Year: 1991
Publication Date: 1991-07-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 148
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