Abstract: A novel low power binary phase shift keying (BPSK) demodulator architecture is presented. The design employs a phase frequency detector (PFD) based phase locked loop (PLL), which allows for low power consumption and a higher tracking and locking range compared to prior art. Using the proposed architecture, a 13.5 MHz BPSK demodulator has been designed and fabricated in a 0.5mum CMOS technology. Simulation and chip measurement result show that this BPSK demodulator provides low power operation and robust performance.
Publication Year: 2007
Publication Date: 2007-05-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 6
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