Title: A software pipelining algorithm in high-level synthesis for FPGA architectures
Abstract: In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the non-pipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.
Publication Year: 2009
Publication Date: 2009-03-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 8
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