Title: A Robust 0.15pm CMOS Technology with CoSiz Salicide and Shallow Trench Isolation
Abstract: A high performance robust 0.1 Spm CMOS technology is reported. This technology integrates two key processes including (1) a CoSi2 salicide process that realizes higher driving current than TiSi2 process and (2) a newly developed shallow trench isolation (STI) process with suppressed reverse narrow channel effect. The excellent thermal stability of sheet resistance is provided using high temperature sputtered and in-situ annealed CoSi2 salicide. In this process, 12%(PMOS) and 4%(NMOS) higher driving current have been achieved, and the VT has not been lowered down to 0.2pm channel width. The 18.5~~ Tpd has been obtained for an inverter at V~o=l.8V.
Publication Year: 1997
Publication Date: 1997-01-01
Language: en
Type: article
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