Title: Plasma doping for S/D extensions: device integration, gate oxide reliability and dynamic behavior
Abstract: We present in this paper electrical results where the ultra low energy (ULE) implantation is replaced by plasma doping (PLAD) process for the source/drain extensions (SDE) for both PMOS and NMOS devices. We show good I/sub on//I/sub off/ performances (730/spl mu/A//spl mu/m/320/spl mu/A//spl mu/m at Ioff -100nA//spl mu/m) on isolated transistors especially with a gain for NMOS devices and we discuss on the improvement of several "secondary" parameters like SDE resistance or junction leakage. Secondly, gate oxide reliability electrical tests show that PLAD does not damage gate oxide integrity. Finally we demonstrate the improvement of dynamic performance using PLAD through RO measurement.
Publication Year: 2005
Publication Date: 2005-12-13
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot