Title: High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming
Abstract: This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost
Publication Year: 2006
Publication Date: 2006-10-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 67
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