Title: A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation
Abstract: A multi-stage replica bitline technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40-nm process node, this technique achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%.
Publication Year: 2009
Publication Date: 2009-09-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 21
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