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{'id': 'https://openalex.org/W2104456922', 'doi': 'https://doi.org/10.1002/cpe.2954', 'title': 'Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture', 'display_name': 'Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture', 'publication_year': 2012, 'publication_date': '2012-11-22', 'ids': {'openalex': 'https://openalex.org/W2104456922', 'doi': 'https://doi.org/10.1002/cpe.2954', 'mag': '2104456922'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://doi.org/10.1002/cpe.2954', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S11065456', 'display_name': 'Concurrency and Computation Practice and Experience', 'issn_l': '1532-0626', 'issn': ['1532-0626', '1532-0634'], 'is_oa': False, 'is_in_doaj': False, 'is_core': True, 'host_organization': 'https://openalex.org/P4310320595', 'host_organization_name': 'Wiley', 'host_organization_lineage': ['https://openalex.org/P4310320595'], 'host_organization_lineage_names': ['Wiley'], 'type': 'journal'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'article', 'type_crossref': 'journal-article', 'indexed_in': ['crossref'], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5101554659', 'display_name': 'Cheng‐Yu Lee', 'orcid': 'https://orcid.org/0000-0003-4310-5331'}, 'institutions': [{'id': 'https://openalex.org/I148099254', 'display_name': 'National Chung Cheng University', 'ror': 'https://ror.org/0028v3876', 'country_code': 'TW', 'type': 'education', 'lineage': ['https://openalex.org/I148099254']}], 'countries': ['TW'], 'is_corresponding': False, 'raw_author_name': 'Cheng‐Yu Lee', 'raw_affiliation_strings': ['Department of Computer Science and Information Engineering National Chung Cheng University 168, University Rd. Min‐Hsiung Chia‐Yi Taiwan'], 'affiliations': [{'raw_affiliation_string': 'Department of Computer Science and Information Engineering National Chung Cheng University 168, University Rd. Min‐Hsiung Chia‐Yi Taiwan', 'institution_ids': ['https://openalex.org/I148099254']}]}, {'author_position': 'middle', 'author': {'id': 'https://openalex.org/A5078942161', 'display_name': 'Min‐Chin Hung', 'orcid': None}, 'institutions': [{'id': 'https://openalex.org/I148099254', 'display_name': 'National Chung Cheng University', 'ror': 'https://ror.org/0028v3876', 'country_code': 'TW', 'type': 'education', 'lineage': ['https://openalex.org/I148099254']}], 'countries': ['TW'], 'is_corresponding': False, 'raw_author_name': 'Min‐Chin Hung', 'raw_affiliation_strings': ['Department of Computer Science and Information Engineering National Chung Cheng University 168, University Rd. Min‐Hsiung Chia‐Yi Taiwan'], 'affiliations': [{'raw_affiliation_string': 'Department of Computer Science and Information Engineering National Chung Cheng University 168, University Rd. Min‐Hsiung Chia‐Yi Taiwan', 'institution_ids': ['https://openalex.org/I148099254']}]}, {'author_position': 'last', 'author': {'id': 'https://openalex.org/A5102085640', 'display_name': 'Rong‐Guey Chang', 'orcid': None}, 'institutions': [{'id': 'https://openalex.org/I148099254', 'display_name': 'National Chung Cheng University', 'ror': 'https://ror.org/0028v3876', 'country_code': 'TW', 'type': 'education', 'lineage': ['https://openalex.org/I148099254']}], 'countries': ['TW'], 'is_corresponding': False, 'raw_author_name': 'Rong‐Guey Chang', 'raw_affiliation_strings': ['Department of Computer Science and Information Engineering National Chung Cheng University 168, University Rd. Min‐Hsiung Chia‐Yi Taiwan'], 'affiliations': [{'raw_affiliation_string': 'Department of Computer Science and Information Engineering National Chung Cheng University 168, University Rd. Min‐Hsiung Chia‐Yi Taiwan', 'institution_ids': ['https://openalex.org/I148099254']}]}], 'countries_distinct_count': 1, 'institutions_distinct_count': 1, 'corresponding_author_ids': [], 'corresponding_institution_ids': [], 'apc_list': {'value': 4740, 'currency': 'USD', 'value_usd': 4740, 'provenance': 'doaj'}, 'apc_paid': None, 'fwci': 0.0, 'has_fulltext': True, 'fulltext_origin': 'ngrams', 'cited_by_count': 0, 'citation_normalized_percentile': {'value': 0.0, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 0, 'max': 65}, 'biblio': {'volume': '26', 'issue': '1', 'first_page': '134', 'last_page': '151'}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T10904', 'display_name': 'Reconfigurable Computing Systems and Design Methods', 'score': 0.9998, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T10904', 'display_name': 'Reconfigurable Computing Systems and Design Methods', 'score': 0.9998, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10829', 'display_name': 'Networks on Chip in System-on-Chip Design', 'score': 0.9998, 'subfield': {'id': 'https://openalex.org/subfields/1705', 'display_name': 'Computer Networks and Communications'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T10054', 'display_name': 'Parallel Computing and Performance Optimization', 'score': 0.9997, 'subfield': {'id': 'https://openalex.org/subfields/1708', 'display_name': 'Hardware and Architecture'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/processor-register', 'display_name': 'Processor register', 'score': 0.8555857}, {'id': 'https://openalex.org/keywords/application-specific-instruction-set-processor', 'display_name': 'Application-specific instruction-set processor', 'score': 0.6498679}, {'id': 'https://openalex.org/keywords/embedded-systems', 'display_name': 'Embedded Systems', 'score': 0.544486}, {'id': 'https://openalex.org/keywords/instruction-scheduling', 'display_name': 'Instruction scheduling', 'score': 0.53153306}, {'id': 'https://openalex.org/keywords/processor-design', 'display_name': 'Processor design', 'score': 0.52127576}, {'id': 'https://openalex.org/keywords/reconfigurable-computing', 'display_name': 'Reconfigurable Computing', 'score': 0.51912}, {'id': 'https://openalex.org/keywords/media-processor', 'display_name': 'Media processor', 'score': 0.4909568}, {'id': 'https://openalex.org/keywords/register-file', 'display_name': 'Register file', 'score': 0.4792614}, {'id': 'https://openalex.org/keywords/pipeline-burst-cache', 'display_name': 'Pipeline burst cache', 'score': 0.45566928}, {'id': 'https://openalex.org/keywords/register-allocation', 'display_name': 'Register allocation', 'score': 0.44019452}], 'concepts': [{'id': 'https://openalex.org/C170595534', 'wikidata': 'https://www.wikidata.org/wiki/Q249743', 'display_name': 'Very long instruction word', 'level': 2, 'score': 0.9127821}, {'id': 'https://openalex.org/C2871975', 'wikidata': 'https://www.wikidata.org/wiki/Q187466', 'display_name': 'Processor register', 'level': 4, 'score': 0.8555857}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.7960264}, {'id': 'https://openalex.org/C201736964', 'wikidata': 'https://www.wikidata.org/wiki/Q621583', 'display_name': 'Application-specific instruction-set processor', 'level': 3, 'score': 0.6498679}, {'id': 'https://openalex.org/C161611012', 'wikidata': 'https://www.wikidata.org/wiki/Q106370', 'display_name': 'Digital signal processor', 'level': 3, 'score': 0.6492901}, {'id': 'https://openalex.org/C202491316', 'wikidata': 'https://www.wikidata.org/wiki/Q272683', 'display_name': 'Instruction set', 'level': 2, 'score': 0.6100402}, {'id': 'https://openalex.org/C118524514', 'wikidata': 'https://www.wikidata.org/wiki/Q173212', 'display_name': 'Computer architecture', 'level': 1, 'score': 0.5672674}, {'id': 'https://openalex.org/C73564150', 'wikidata': 'https://www.wikidata.org/wiki/Q11417093', 'display_name': 'Instruction scheduling', 'level': 5, 'score': 0.53153306}, {'id': 'https://openalex.org/C526435321', 'wikidata': 'https://www.wikidata.org/wiki/Q1303814', 'display_name': 'Processor design', 'level': 2, 'score': 0.52127576}, {'id': 'https://openalex.org/C52027705', 'wikidata': 'https://www.wikidata.org/wiki/Q6805986', 'display_name': 'Media processor', 'level': 4, 'score': 0.4909568}, {'id': 'https://openalex.org/C117280010', 'wikidata': 'https://www.wikidata.org/wiki/Q180944', 'display_name': 'Register file', 'level': 3, 'score': 0.4792614}, {'id': 'https://openalex.org/C173608175', 'wikidata': 'https://www.wikidata.org/wiki/Q232661', 'display_name': 'Parallel computing', 'level': 1, 'score': 0.474289}, {'id': 'https://openalex.org/C206729178', 'wikidata': 'https://www.wikidata.org/wiki/Q2271896', 'display_name': 'Scheduling (production processes)', 'level': 2, 'score': 0.45764866}, {'id': 'https://openalex.org/C157547923', 'wikidata': 'https://www.wikidata.org/wiki/Q7197276', 'display_name': 'Pipeline burst cache', 'level': 5, 'score': 0.45566928}, {'id': 'https://openalex.org/C123657996', 'wikidata': 'https://www.wikidata.org/wiki/Q12271', 'display_name': 'Architecture', 'level': 2, 'score': 0.4434573}, {'id': 'https://openalex.org/C128916667', 'wikidata': 'https://www.wikidata.org/wiki/Q1343660', 'display_name': 'Register allocation', 'level': 3, 'score': 0.44019452}, {'id': 'https://openalex.org/C84462506', 'wikidata': 'https://www.wikidata.org/wiki/Q173142', 'display_name': 'Digital signal processing', 'level': 2, 'score': 0.32360113}, {'id': 'https://openalex.org/C9390403', 'wikidata': 'https://www.wikidata.org/wiki/Q3966', 'display_name': 'Computer hardware', 'level': 1, 'score': 0.26926202}, {'id': 'https://openalex.org/C111919701', 'wikidata': 'https://www.wikidata.org/wiki/Q9135', 'display_name': 'Operating system', 'level': 1, 'score': 0.18885022}, {'id': 'https://openalex.org/C153247305', 'wikidata': 'https://www.wikidata.org/wiki/Q835713', 'display_name': 'Memory address', 'level': 3, 'score': 0.16088781}, {'id': 'https://openalex.org/C98986596', 'wikidata': 'https://www.wikidata.org/wiki/Q1143031', 'display_name': 'Semiconductor memory', 'level': 2, 'score': 0.1548034}, {'id': 'https://openalex.org/C107568181', 'wikidata': 'https://www.wikidata.org/wiki/Q5319000', 'display_name': 'Dynamic priority scheduling', 'level': 3, 'score': 0.11310977}, {'id': 'https://openalex.org/C169590947', 'wikidata': 'https://www.wikidata.org/wiki/Q47506', 'display_name': 'Compiler', 'level': 2, 'score': 0.11160222}, {'id': 'https://openalex.org/C189783530', 'wikidata': 'https://www.wikidata.org/wiki/Q352090', 'display_name': 'CPU cache', 'level': 3, 'score': 0.10489449}, {'id': 'https://openalex.org/C68387754', 'wikidata': 'https://www.wikidata.org/wiki/Q7271585', 'display_name': 'Schedule', 'level': 2, 'score': 0.07515058}, {'id': 'https://openalex.org/C127413603', 'wikidata': 'https://www.wikidata.org/wiki/Q11023', 'display_name': 'Engineering', 'level': 0, 'score': 0.07354629}, {'id': 'https://openalex.org/C119948110', 'wikidata': 'https://www.wikidata.org/wiki/Q7858726', 'display_name': 'Two-level scheduling', 'level': 4, 'score': 0.07038236}, {'id': 'https://openalex.org/C142362112', 'wikidata': 'https://www.wikidata.org/wiki/Q735', 'display_name': 'Art', 'level': 0, 'score': 0.0}, {'id': 'https://openalex.org/C21547014', 'wikidata': 'https://www.wikidata.org/wiki/Q1423657', 'display_name': 'Operations management', 'level': 1, 'score': 0.0}, {'id': 'https://openalex.org/C115537543', 'wikidata': 'https://www.wikidata.org/wiki/Q165596', 'display_name': 'Cache', 'level': 2, 'score': 0.0}, {'id': 'https://openalex.org/C153349607', 'wikidata': 'https://www.wikidata.org/wiki/Q36649', 'display_name': 'Visual arts', 'level': 1, 'score': 0.0}, {'id': 'https://openalex.org/C201148951', 'wikidata': 'https://www.wikidata.org/wiki/Q5015976', 'display_name': 'Cache coloring', 'level': 4, 'score': 0.0}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://doi.org/10.1002/cpe.2954', 'pdf_url': None, 'source': {'id': 'https://openalex.org/S11065456', 'display_name': 'Concurrency and Computation Practice and Experience', 'issn_l': '1532-0626', 'issn': ['1532-0626', '1532-0634'], 'is_oa': False, 'is_in_doaj': False, 'is_core': True, 'host_organization': 'https://openalex.org/P4310320595', 'host_organization_name': 'Wiley', 'host_organization_lineage': ['https://openalex.org/P4310320595'], 'host_organization_lineage_names': ['Wiley'], 'type': 'journal'}, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [{'id': 'https://metadata.un.org/sdg/9', 'display_name': 'Industry, innovation and infrastructure', 'score': 0.45}], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 17, 'referenced_works': ['https://openalex.org/W1967889241', 'https://openalex.org/W2066670963', 'https://openalex.org/W2078396000', 'https://openalex.org/W2111377238', 'https://openalex.org/W2128377351', 'https://openalex.org/W2170886848', 'https://openalex.org/W2543996155', 'https://openalex.org/W4235414243', 'https://openalex.org/W4235719931', 'https://openalex.org/W4236453383', 'https://openalex.org/W4237382706', 'https://openalex.org/W4239187837', 'https://openalex.org/W4239583065', 'https://openalex.org/W4240994858', 'https://openalex.org/W4242172296', 'https://openalex.org/W4242383623', 'https://openalex.org/W4245563104'], 'related_works': ['https://openalex.org/W788020894', 'https://openalex.org/W3116750762', 'https://openalex.org/W2556885209', 'https://openalex.org/W2386145041', 'https://openalex.org/W2169574597', 'https://openalex.org/W2149733668', 'https://openalex.org/W2127482451', 'https://openalex.org/W2104456922', 'https://openalex.org/W2005778825', 'https://openalex.org/W104139514'], 'abstract_inverted_index': {'SUMMARY': [0], 'The': [1, 14, 105], 'popularity': [2], 'of': [3, 47, 49, 65, 78], 'multimedia': [4, 19], 'applications': [5], 'made': [6], 'them': [7], 'a': [8, 94], 'major': [9], 'theme': [10], 'in': [11, 143], 'embedded': [12, 23, 32], 'systems.': [13], 'key': [15, 42], 'component': [16], 'for': [17], 'supporting': [18], 'application': [20], 'well': [21, 61], 'is': [22, 83, 140], 'processor.': [24], 'Thus,': [25], 'we': [26, 92], 'have': [27], 'designed': [28], 'and': [29, 55, 69, 96, 110, 117, 124, 145], 'implemented': [30], 'an': [31, 75], 'processor,': [33, 36], 'called': [34], 'UniDual': [35, 79], 'to': [37, 85, 100], 'achieve': [38], 'this': [39, 90], 'objective.': [40], 'Its': [41], 'features': [43], 'are': [44], 'the': [45, 63, 102, 131, 134], 'integration': [46], 'instructions': [48, 109, 114, 119], 'reduced': [50], 'instruction': [51, 67, 97], 'set': [52, 68], 'computers': [53], '(RISCs)': [54], 'digital': [56], 'signal': [57], 'processors': [58], '(DSPs)': [59], 'as': [60, 62], 'support': [64], 'special': [66], 'shared‐based': [70], 'clustered': [71], 'register': [72], 'architecture.': [73], 'However,': [74], 'important': [76], 'issue': [77], 'that': [80, 137], 'remains': [81], 'open': [82], 'how': [84], 'efficiently': [86], 'allocate': [87], 'registers.': [88], 'In': [89], 'paper,': [91], 'present': [93], 'scheduling': [95], 'transformation': [98], 'approach': [99, 107], 'resolve': [101], 'aforementioned': [103], 'issue.': [104], 'proposed': [106], 'schedules': [108], 'then': [111], 'transforms': [112], 'overlapped': [113], 'into': [115, 127], 'RISC': [116], 'DSP': [118], 'by': [120], 'taking': [121], 'communication': [122], 'overhead': [123], 'hardware': [125], 'limitations': [126], 'account.': [128], 'Compared': [129], 'with': [130], 'greedy': [132], 'approach,': [133], 'evaluation': [135], 'shows': [136], 'our': [138], 'work': [139], 'relatively': [141], 'effective': [142], 'performance': [144], 'code': [146], 'size': [147], 'reduction.': [148], 'Copyright': [149], '©': [150], '2012': [151], 'John': [152], 'Wiley': [153], '&': [154], 'Sons,': [155], 'Ltd.': [156]}, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W2104456922', 'counts_by_year': [], 'updated_date': '2024-08-22T04:37:38.524922', 'created_date': '2016-06-24'}