Abstract: This paper presents an 8-bit Flash Analog-to-Digital converter (ADC) implemented in 0.18-μm CMOS process. Different from the conventional Flash ADCs, we use a single MOS comparator technique to replace the traditional comparator. Therefore, our method can reduce a lot of transistor numbers, chip area, power consumption for higher resolution. The designed Flash ADC consumes only 0.54 mW from a 1.8V power supply. The speed of this design is 1.4GS/s. The simulated static differential non-linearity error (DNL) and integral non-linearity error (INL) are between 0.4/-0.4 LSB and 0.42/-0.55 LSB, respectively.
Publication Year: 2011
Publication Date: 2011-12-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 1
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot