Title: High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs
Abstract: This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SSADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SSADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 ㎒ clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 ㎽ with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a 0.13 μm CMOS process.
Publication Year: 2015
Publication Date: 2015-02-28
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 1
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