Title: FPGA programmable logic block evaluation using quantified Boolean satisfiability
Abstract: A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.
Publication Year: 2006
Publication Date: 2006-01-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 6
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