Title: Symmetric and asymmetric transformer based cascaded multilevel inverter with minimum number of components
Abstract: IET Power ElectronicsVolume 8, Issue 6 p. 1052-1060 Research ArticlesFree Access Symmetric and asymmetric transformer based cascaded multilevel inverter with minimum number of components Amir Farakhor, Amir Farakhor Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this authorRouzbeh Reza Ahrabi, Rouzbeh Reza Ahrabi Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this authorHossein Ardi, Hossein Ardi Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this authorSajad Najafi Ravadanegh, Corresponding Author Sajad Najafi Ravadanegh [email protected] Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this author Amir Farakhor, Amir Farakhor Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this authorRouzbeh Reza Ahrabi, Rouzbeh Reza Ahrabi Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this authorHossein Ardi, Hossein Ardi Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this authorSajad Najafi Ravadanegh, Corresponding Author Sajad Najafi Ravadanegh [email protected] Smart Distribution Grid Research Lab., Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, IranSearch for more papers by this author First published: 01 June 2015 https://doi.org/10.1049/iet-pel.2014.0378Citations: 42AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract In this study, a novel transformer based cascaded multilevel inverter is presented. The proposed inverter can operate in both symmetric and asymmetric topologies. The presented inverter benefits from the advantages such as reduced number of power switches and reduced total peak inverse voltage of the switching components. The numbers of insulated gate driver circuits are also decreased with respect to the power switches. Furthermore, the presented topology requires just a single DC source. In addition, the numbers of on-state switches in the current paths are reduced. Therefore the voltage drops across the switches are mitigated and as a result the efficiency of the presented inverter is improved. The mentioned advantages cause the implementation cost to be reduced. The operation of the converter is discussed thoroughly for both symmetric and asymmetric operations. The feasibility of the presented inverter topology is validated using the simulation results. Experimental results under 1.5 kW are also added to justify the theoretical analyses. 1 Introduction In the past few years, multilevel inverters have played a crucial role in most systems such as renewable energy power generation systems, large motor drives, power quality improvement devices such as dynamic voltage restorer and flexible AC transmission systems [1-3]. Hence, multilevel inverters have attracted great attention of power electronic researchers. Multilevel inverters have various advantages such as lower switching losses, stepwise output voltage, smaller common mode voltage and lower peak inverse voltage (PIV) on main switches [4-6]. These advantages make multilevel inverters promising for many industrial applications. There are mainly three multilevel converter topologies: diode-clamped [7], flying capacitor [8] and cascaded H-bridge with independent DC sources [9]. They provide stepwise voltage with high quality. However, their main disadvantage, which is the excessive number of switching components, limits their applications. In diode-clamped configuration, regulating the capacitors voltages makes the control method intricate. Moreover, extensive numbers of clamping diodes are required in this topology. Ladder structure of capacitors is used in flying capacitor multilevel inverters. Thus, the volume of the system is enlarged because of the necessity for more capacitors. Cascaded H-bridge structure has the advantage of being modular which makes this structure easily expandable for higher number of output voltage levels. However, the need for separate DC voltage sources for each module and the number of switching components are the main disadvantages for this configuration. For overcoming these problems, novel topologies of multilevel inverters are presented in recent years [10-17]. In [10], an inverter structure is proposed which requires several isolated DC voltage sources with unequal values which make the implementation and realisation of the presented structure difficult. In [11], a multilevel structure is presented which can only produce positive voltage levels. An H-bridge module is used at the final stage of the circuit to produce the negative and zero voltage levels too. However, the power switches used in the H-bridge nodule suffer from high PIV. In [13], a multilevel structure with reduced number of switches is presented which can only operate in symmetric mode. Another structure is presented in [14] which have the disadvantage of high total PIV of the switching devices. In [18], novel three-phase asymmetrical cascaded multilevel voltage source inverter is presented. The number of on-state switches, insulated gate driver circuits, PIV on main switches and cost are reduced. In some papers such as [15-17], the numbers of switches are reduced. However, the number of switches still can be reduced. Switching strategies of multilevel inverters are categorised into high switching frequency methods such as sinusoidal pulse width modulation (SPWM) strategy [19, 20] and low switching frequency techniques, often equal to fundamental switching frequency of the components, which create stepwise output voltage waveform [21]. Second category comprises of three major switching strategies so called ‘optimised harmonic stepped waveform’ [22], ‘selective harmonic mitigation PWM’ [23] and ‘optimal minimisation of the THD’ [24]. Some other control methods of multilevel inverters such as digital control [25] and voltage vector approximation control [26] are discussed in recently published articles. In this paper, SPWM strategy is employed for the presented inverter. To solve aforementioned problems of the previous works, a transformer based cascaded multilevel inverter is proposed in this paper. The proposed converter operates in both symmetric and asymmetric topologies. The advantages of the proposed converter can be described as The circuit components are reduced. PIV of the switches is decreased. The on-state switches through the current paths are also reduced. The efficiency is improved. Finally, to justify the theoretical analysis a hardware prototype is implemented in laboratory. The experimental results show the practicality of the presented inverter structure. 2 Proposed inverter topology The circuit structure of the proposed inverter is shown in Fig. 1. Fig. 1a depicts the extendable modular structure of the presented converter and Fig. 1b gives the two-module configuration which is used for analysis of the presented inverter. As it is shown in Fig. 1a, the presented inverter consists of a single DC source, two capacitors to split the input voltage, some unidirectional power switches, some bidirectional power switches and several low-frequency transformers. In the given circuit structure, if the turn ratios of the transformers are equal, symmetrical topology will be obtained. Otherwise, asymmetrical topology will be resulted. According to Fig. 1a, the power switches Sna and Snb(n = 1,2,…) should not be turned on simultaneously to avoid the occurrence of any short circuits. The bidirectional power switches are also used to determine the connection configuration of the primary sides of the transformers. The secondary sides of the transformers are series-connected to synthesise the output voltage. Using proper switching strategy, the presented inverter can generate the desired output voltage with high quality. The proposed structure is able to produce positive, zero and negative voltages. Therefore an H-bridge module at the output stage is not required zero and negative voltages. Some inverters such as one presented in [14] requires an H-bridge module to produce zero and negative voltages. This is a main disadvantage for this inverter since the power switches in the H-bridge module have high PIV. Assuming n as the number of the modules in the presented inverter, the number of transformers, switch units, IGBTs and gate drivers can be determined as follows (1) (2) (3) Fig. 1Open in figure viewerPowerPoint Circuit structure of the proposed inverter a Presented modular cascaded multilevel inverter b Presented cascaded multilevel inverter under study It is considered that each bidirectional switch consists of two IGBTs and two anti-parallel diodes. Each module in the presented converter can generate five voltage levels. If the turn ratios of the transformers are all one (Ns/Np = 1), these voltages will be −2VDC, −VDC, 0, +VDC and +2VDC. In the following sections, symmetrical and asymmetrical topologies are analysed thoroughly. To simplify the analysis, two-module inverter structure is considered as shown in Fig. 1b. 2.1 Symmetric topology analysis The symmetric topology of the presented inverter will be achieved if the turn ratios of all the transformers are considered all the same. Here the turn ratios of all the transformers are considered 1:1. Capacitors are used to split the input voltage as shown in Fig. 1b. It is considered that the voltage of the DC source is 2VDC and the voltages on the capacitors are VDC. Table 1 shows the proper switching patterns to obtain various output voltages. As it is shown in Table 1, the presented structure can generate positive, zero and negative output voltages. For instance, in the first module shown in Fig. 1b, there are four possible switching states for switches S1 and S2. If S1 is turned on and S2 is turned off, the primary side of the transformer T1 will be short circuited and generate a zero voltage. However, the primary side of the transformer T2 will have the voltage provided from the upper side of the circuit. If S1 is turned off and S2 is turned on, both transformers T1 and T2 will be connected in parallel and they will both have the voltage provided from the upper side of the circuit. If both switches S1 and S2 are turned on simultaneously, the primary side of the transformers will be short circuited and the module will generate the zero voltage. The remaining possible switching state when both switches are turned off is an undesired switching state. In addition, in the upper side of the first module, if switch S1a is turned on the positive voltage will be applied to the transformers. If switch S1b is turned on, the negative voltage will be applied to the transformers. If none of the switches is turned on, no voltages will be provided for the transformers. Switches S1a and S1b cannot be turned on simultaneously to avoid any short circuits. Considering m as the number of output voltage levels, the number of transformers, switch units and gate drivers, IGBTs can be determined as follows (4) (5) (6) Table 1. Output voltage for different states of switches for the symmetric proposed multilevel inverter Vout S1a S1b S2a S2b S1 S2 S3 S4 4VDC off on off on off on off on 3VDC off on off on off on on off 2VDC off on off off off on on on VDC off on off off on off on on 0 off off off off on on on on −VDC off off on off on on on off −2VDC off off on off on on off on −3VDC on off on off on off off on −4VDC on off on off off on off on Moreover, the total PIV of the switching devices and the number of on-state switching in the current flow path can be given as below (7) (8)It is worth noting that the presented inverter structure is not able to generate output voltages with 7 + 4i(i = 0,1,…N) levels. However, this issue does not serve as a disadvantage for the presented inverter since the structure is able to generate output voltages with higher number of levels. 2.2 Asymmetric topology analysis Turn ratios of the transformers can be selected in a way that the numbers of output voltage levels are maximised. In asymmetrical topology, higher output voltage levels can be achieved by using fewer transformers and other components. In the presented inverter, the turn ratios of the transformers are chosen to be 1:5n−1 where n is the number of the module in which the transformer is located. For instance, in the asymmetrical topology of the inverter shown in Fig. 1b, Turn ratios of the transformers will be in the following way: T1 (1:1), T2 (1:1), T3 (1:5), T4 (1:5). It is worth to note that other turn ratios for the transformers are possible too. However, utilising the aforementioned technique for the turn ratios of the transformers will result in the maximum output voltage levels. Table 2 shows the proper switching patterns to obtain different output voltage levels. As it is shown in Table 2, the presented inverter is able to generate all possible output voltage levels. Using asymmetrical structure, it is possible to obtain higher output voltage levels and to make an efficient use from the transformers. Considering m as the number of output voltage levels, the number of transformers, switch units and gate drivers, IGBTs in the asymmetrical structure can be determined as follows (9) (10) (11) Table 2. Output voltage for different states of switches for the asymmetric proposed multilevel inverter Vout S1a S1b S2a S2b S1 S2 S3 S4 12VDC off on off on off on off on 11VDC off on off on on off off on 10VDC off off off on on on off on 9VDC on off off on on off off on 8VDC on off off on off on off on 7VDC off on off on off on on off 6VDC off on off on on off on off 5VDC off off off on on on on off 4VDC on off off on on off on off 3VDC on off off on off on on off 2VDC off on off off off on on on VDC off on off off on off on on 0 off off off off on on on on −VDC on off off off on off on on −2VDC on off off off off on on on −3VDC off on on off off on on off −4VDC off on on off on off on off −5VDC off off on off on on on off −6VDC on off on off on off on off −7VDC on off on off off on on off −8VDC off on on off off on off on −9VDC off on on off on off off on −10VDC off off on off on on off on −11VDC on off on off on off off on −12VDC on off on off off on off on Moreover, the total PIV of the switching devices and the number of on-state switching in the current flow path can be given as below (12) (13) 2.3 Comparison study Various structures for multilevel inverters have been presented in recent years. The proposed inverter is compared with some of the recent presented structures. In some structures, different DC sources with unequal voltages (asymmetric topology) are used to obtain more output voltage level [13, 15]. However, implementations of these structures are difficult since several DC sources with different voltages are required. Furthermore, by using equal DC sources (symmetric topology), the number of output voltage levels will be reduced. One of the main advantages of the presented inverter is that it only requires a single DC source in both symmetric and asymmetric topologies. Therefore the implementation and realisation will be much easier in comparison with topologies with multiple unequal DC sources such as structures in [10, 15]. To clarify the comparison, the circuit configurations of the compared structures are shown in Fig. 2. Fig. 2Open in figure viewerPowerPoint Circuit configuration of the structures a Inverter in [12] b Inverter in [15] The numbers of the switch units or gate drivers are also reduced in the presented inverter. Fig. 3a shows the comparison of the switch units or gate drivers with some other structures. As it is shown in Fig. 3a, in both symmetric and asymmetric topologies, the presented inverter requires fewer numbers of gate drivers. For instance, for a 25-level inverter, the presented inverter utilises 24 and 8 gate drivers in symmetric and asymmetric topologies, respectively. However, in the cascaded H-bridge multilevel inverter 48 gate drivers are required. Reduction of the gate drivers reduces the overall implementation cost and increases the system reliability. The numbers of IGBTs are also reduced in the presented inverter. Fig. 3b shows the comparison of the IGBT numbers with some recently presented structures. As shown in Fig. 3b, the asymmetric topology of the presented inverter requires fewer numbers of the IGBTs. For example, for a 25-level inverter, the presented inverter utilises 12 IGBTs in asymmetric topology. However, the structure presented in [15] requires 28 IGBTs. Fig. 3Open in figure viewerPowerPoint Comparison of the proposed topology with some other topologies a Number of switch units and gate drivers b Number of IGBTs c Number of on-state switches d Normalised total PIV of the switches e Number of transformers f Number of input voltages Another criterion to assess the performance of the multilevel inverters is the number of on-state switches in the current flow path. Fig. 3c depicts the comparison of the numbers of on-state switches with some inverter configurations. The fewer number of on-state switches decreases the voltage drops across the switches. Therefore the efficiency is increased. In addition, the PIV of all switches are an important criterion to choose the proper switches. The PIV of the switches are also compared in Fig. 3d. The PIV of the presented inverter in asymmetric operation is less than the other structures. In addition, the summarised characteristics of the presented inverter and the structure presented before are given in Table 3. The comparison of the presented structure and the other structures indicates the superiority of the presented inverter structure. Table 3. Comparison of the presented inverter with other structures Conventional cascaded H-bridge Reference [12] Reference [15] Proposed symmetric Proposed asymmetric number of IGBTs 2(m − 1) m + 1 m + 3 number of gate drivers 2(m − 1) m + 1 m + 3 m − 1 number of on-state switches m − 1 m − 1 total PIV on switches 2(m – 1)VDC (m + 1)VDC 3(m – 1)VDC 3 Efficiency analysis Non-ideal power switches face two kinds of losses, conduction losses and switching losses. Switching losses, equivalent resistant of switches and voltage drop on on-state switches should be considered if the power switches are non-ideal. The conduction and switching losses of the presented inverter are discussed as follows. 3.1 Conduction losses To calculate conduction losses, first conduction losses of the typical transistor and diode is calculated then they are extended to multilevel inverter structure. Von, T and Von, D are on-state voltage of transistor and diode, respectively. i(t) is considered as instantaneous current. The conduction loss of transistor and diode are defined as (14) (15)RT and RD are the equivalent resistances of the transistor and diode, respectively. β is constant which is related to specification of the transistor. The output voltage level determines the numbers of switches (IGBT and diode) which are in current path. In symmetric operation state, in the worst condition four IGBTs and two diodes are in current path. Proposed multilevel inverter conduction power loss is (16)Considering the output current in sinusoidal, the current which flows through switches is defined as (17)Using (16) and (17), the proposed inverter conduction power loss is formulated as (18)In asymmetric structure, in the worst condition four IGBTs and two diodes are in current path just same as symmetric operation state. Equation (16) is also valid for the conduction power losses of the proposed inverter in asymmetric structure. However various current flows through switches base on turn ratio of the transformers as follows (19)where N is turn ratio of the transformers in each module. In this paper, N is one for first module and five for second module as an example. Then conduction power loss in asymmetric structure is determined as (20) 3.2 Switching losses Switching losses for a typical switch are calculated and then applied to proposed inverter. Fig. 4a shows linear estimation of voltage and current of power switches during turn-on time. Turn-on losses of switches are obtained as (21)where EOn,s is turn-on loss of switch S, tOn is the turn-on time of the switch, I is the current through switch after turning on and VSw,s is on-state voltage of switch. Fig. 4b shows linear estimation of voltage and current for power switches during turn-off time and then turn-off losses of switches are obtained as (22)where EOff,s is turn-off loss of switch S, tOff is the turn off time of switch, I is the current through switch after turning off and VSw,s is off-state voltage of switch. Fig. 4Open in figure viewerPowerPoint Voltage and current waveforms of switch during on and off state a Turning on b Turning off Considering fundamental switching for proposed inverter, in symmetric and asymmetric structures, switching losses are different. In symmetric structure, S2 and S4 face maximum frequency of switching, each one 2 times in half period, hence switching losses for symmetric structure is (23)where m is level of output voltage, f is switching frequency. In asymmetric operation, first module frequency is m/5. To show losses in asymmetric structure, all switches are considered to be fulfilled in maximum frequency of switches in each operation which depends on output voltage level. Therefore the power losses can be formulated as follows (24) 3.3 Transformer losses The total power losses of a transformer can be expressed as below (25)where PC is the total core losses and PW is the total copper losses of a transformer. The total core losses of a transformer can be written as (26)where KC and β are constants, which are dependent on the core material and operating principle. AC is the sectional area of the core, lm is the length of the magnetic path. ΔB is also the peak flux density. We can also express the ΔB as follows (27)where λ1 is the voltage time area applied to the primary side of the transformer and n1 is the number of turns in the primary side of the transformer. Copper losses should also be considered in the transformer loss calculations. The copper losses of a transformer can be written as below (28)where MLT is the mean length of turn, WA is the winding area and ku is the copper fill factor. The Itot can be expressed as follows (29)In addition, the proximity and skin effect is considered and included in ρ. The total loss of the transformer can now be calculated which is the sum of copper loss and the core loss of a transformer. Moreover, in [27], a more detailed analysis and loss calculation is discussed. With considering (14)–(29), we have (30)Fig. 5 represents efficiency for proposed inverter with respect to the output voltage levels. It is shown in Fig. 5 that as the number of voltage levels increases, the number of switching components and transformers increases which results in a lower conversion efficiency. Fig. 5Open in figure viewerPowerPoint Efficiency of proposed inverter in different output voltage levels 4 Simulation results To verify the feasibility of the presented inverter, structure shown in Fig. 1b is simulated by MATLAB Simulink software. The simulations are done for both symmetric and asymmetric topologies. The power switches are treated as ideal in all simulations. The load resistance and inductance are 20 Ω and 55 mH and 45 Ω and 55 mH for symmetric and asymmetric topologies, respectively. The frequency of the output voltage is 50 Hz. In the first case, symmetric topology, the turn ratios of the transformers are considered to be 1:1. Moreover, the DC voltage link is 100 V. Different modulation strategies can be used in multilevel inverters. In this case, SPWM strategy is used as shown in Fig. 6. In this method, carriers are compared with a sinusoidal reference waveform and switching signals is sent to switches. Fig. 6Open in figure viewerPowerPoint Waveforms of the carriers and the reference Fig. 7 shows the output voltage and current waveforms. As it can be seen from Fig. 7a, nine-level output voltage waveform is well generated. The THD of the output voltage is about 13%. The voltages of the secondary sides of all transformers are shown in Fig. 8. Since the secondary sides of the transformers are series-connected, the output voltage is the sum of the transformers’ output voltages. Fig. 7Open in figure viewerPowerPoint Waveforms of the symmetric topology with SPWM a Output voltage b Output current Fig. 8Open in figure viewerPowerPoint Output voltages of the secondary sides of the transformers in symmetric topology a Transformer T1 b Transformer T2 c Transformer T3 d Transformer T4 In the second case, asymmetric topology is simulated where the turn ratios of the transformers are considered to be T1 (1:1), T2 (1:1), T3 (1:5), T4 (1:5). In this case, the fundamental switching strategy is used. Table 2 is used to apply the proper switching signals to the main switches. The DC link voltage is considered to be 60 V. The output voltage and current of the inverter are shown in Fig. 9. As it is shown in Fig. 9a, the presented inverter is able to produce all 25 possible output voltage levels. The THD of the output voltage is about 4.2%. The voltages of the secondary sides of all transformers are shown in Fig. 10. Since the secondary sides of the transformers are series-connected, the output voltage is the sum of the transformers output voltages. It is worth noting that the calculation of the optimal switching angles to minimise the THD of the output voltage is not the objective of this paper. Fig. 9Open in figure viewerPowerPoint Waveforms of the asymmetric topology a Output voltage b Output current Fig. 10Open in figure viewerPowerPoint Output voltages of the secondary sides of the transformers in asymmetric topology a Transformer T1 b Transformer T2 c Transformer T3 d transformer T4 5 Experimental results The experimental results are used to justify the simulation results and theoretical analysis of the proposed inverter in both symmetric and asymmetric topologies. The specifications of the implemented circuit are given in Table 4. Capacitors C1 and C2 are circuit elements designed to decrease voltage ripples across them. The capacitor voltages are approximately given by (31) Table 4. Specifications of the implemented prototype Specifications Values transformer core Pc40 ferrite core transformer turn ratios in symmetric T1,2,3,4: 100:100 transformer turn ratios in asymmetric T1,2: 100:100, T3,4: 100:500 output voltage frequency F = 50 Hz capacitors C1, C2 1000 µF power switch (IGBT) H25R1202 output power 1500 W That ΔQmax is the maximum decrease in charge during the time interval from zero to DT. is the voltage ripple across the capacitors. fS is also the output voltage frequency. Rearranging (31) gives (32)where Cmin is the minimum value for capacitors with the acceptable voltage ripple of . Input DC voltage is 100 and 60 V in symmetric and asymmetric topologies, respectively. The load is taken to be 20 Ω and 55 mH and 45 Ω and 55 mH for symmetric and asymmetric topologies, respectively. Peak value of output voltage for symmetric topologies is 200 V and peak value of output voltage for asymmetric topologies is 360 V. Output voltage levels in symmetric and asymmetric operation states are 9 and 25, respectively. The THD of the output voltages in symmetric and asymmetric operation modes are about 14.5% and 5.8%, respectively. 12 IGBTs and 8 gate drivers in both symmetric and asymmetric structures are used. The IGBTs of prototype circuit are H25R1202 with internal anti-parallel diodes. Figs. 11a and b shows the output voltage and current of the proposed converter in symmetric and asymmetric topologies, respectively. As shown in Fig. 11, the presented inverter is able to generate the all possible output voltage levels. Fig. 11Open in figure viewerPowerPoint Output voltages and currents a 9-level symmetric b 25-level asymmetric 6 Conclusion In this paper, a transformer based cascaded multilevel inverter is proposed. The presented converter can operate in both symmetric and asymmetric topologies. The circuit components of the proposed converter are reduced. However, PIV of the switches is not increased. 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