Title: The architecture comparison and the VLSI implementation of the 32 bit embedded RISC
Abstract: In order to achieve our design goal as a low-cost and high-performance microprocessor, we compared several aspects of the popular embedded RISC architecture, such as general-purpose register file and stack-based, three-stages pipeline and five-stages one, Von Neumman architecture and Harvard counterpart, etc. By these comparisons, we adopted the most suitable architecture sets: a Harvard five-stages pipeline with a set of general-purpose register file. We also verified our design on the Aptix System Explorer MP3CF hardware verification platform and implemented on CSMC 0.6 mm CMOS process.
Publication Year: 2003
Publication Date: 2003-01-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 2
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