Title: A Signature-Based Power Model for MPSoC on FPGA
Abstract: This paper presents a framework for high‐level power estimation of multiprocessor systems‐on‐chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction‐set simulator (ISS)‐based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system‐level design space exploration. We integrated the power estimation technique in a system‐level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex‐6 FPGA board.