Title: FPGA implementation of fast QR decomposition based on givens rotation
Abstract: In this paper, an improved fixed-point hardware design of QR decomposition, specifically optimized for Xilinx FPGAs is introduced. A Givens Rotation algorithm is implemented by using a folded systolic array and the CORDIC algorithm, making this very suitable for high-speed FPGAs or ASIC designs. We improve the internal cell structure so that the system can run at 246MHz with nearly 24M updates per second throughout on a Virtex5 FPGA. The matrix size can be easily scaled up.
Publication Year: 2012
Publication Date: 2012-08-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 34
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