Title: New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm
Abstract: A new algorithm for the multiplication of two elements in GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) based on the modified Booth's algorithm is presented. The proposed algorithm permits efficient realization of the multiplexer-based bit-parallel multiplication using iterative arrays. The latency of the multiplier has 3m/2 clock cycles. For the estimated complexity of the proposed multiplier, we take into the transistor count using a standard CMOS VLSI realization. Our analysis shows that, in terms of the time and the space complexities, the multiplexer-based array architecture is the better choice for our proposed bit-parallel systolic multiplier
Publication Year: 2006
Publication Date: 2006-12-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 3
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