Title: Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET
Abstract: Device design using body-tied fin field effect transistor (bulk FinFET) was considered for the application to 50 nm DRAM technology. We concentrated on the device characteristics such as threshold voltage ( V th ), off-state leakage current ( I off ), subthreshold swing (S.S), and drain induced barrier lowering (DIBL) by controlling lightly doped drain (LDD) profile of the bulk FinFET. Bulk FinFETs with 0 to 3 nm non-overlap between source/drain (S/D) to gate electrode show lower I off , S.S, and DIBL than those with an overlap while maintaining reasonable threshold voltage. We also compared characteristics of the triple gate bulk FinFET with those of the double gate bulk FinFET. Finally, electrical characteristics with LDD doping profile, S/D to gate overlap length, top gate oxide thickness, body doping concentration, fin top doping concentration, and doping profile from the edge to the center of the fin body are also compared.
Publication Year: 2005
Publication Date: 2005-04-01
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 7
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