Title: A System Exploration Platform for Network-on-Chip
Abstract: Network-on-Chip (NoC) is a key component in the design of many cores on a chip. This paper presents a new system level NoC simulation framework, called “Network-On-Chip-centric System Exploration Platform” (NOCSEP). It divides NoC design space into blocks and models them using abstracted layers. Together with task-graph software modeling and simplified middle-layer modeling, it can estimate the performance of an on-chip interconnect rapidly and is therefore very suitable for quickly exploring design alternatives.
Publication Year: 2010
Publication Date: 2010-09-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 5
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