Title: Improved PID controller design for unstable time delay processes based on direct synthesis method and maximum sensitivity
Abstract: AbstractIn this paper, a proportional-integral-derivative controller in series with a lead-lag filter is designed for control of the open-loop unstable processes with time delay based on direct synthesis method. Study of the performance of the designed controllers has been carried out on various unstable processes. Set-point weighting is considered to reduce the undesirable overshoot. The proposed scheme consists of only one tuning parameter, and systematic guidelines are provided for selection of the tuning parameter based on the peak value of the sensitivity function (Ms). Robustness analysis has been carried out based on sensitivity and complementary sensitivity functions. Nominal and robust control performances are achieved with the proposed method and improved closed-loop performances are obtained when compared to the recently reported methods in the literature.Keywords: PID controltime delay systemsrobustnessstabilityunstable process AcknowledgementsThis work was supported by a grant from Department of Science and Technology under fast track scheme for young researchers with grant no. SR/FTP/ETA-030/2009.Additional informationNotes on contributorsB. VanavilB. Vanavil received her bachelor's and master's degrees in Biotechnology from Anna University, Chennai, India, and Kalasalingam University, India, respectively. She is currently working for her PhD in Department of Chemical Engineering, National Institute of Technology, Tiruchirappalli, India, in the area of optimisation and control of bioprocesses. Her research interests include bioprocess engineering, control of unstable systems. Improved PID controller design for unstable time delay processes based on direct synthesis method and maximum sensitivityAll authorsB. Vanavil, K. Krishna Chaitanya & A. Seshagiri Raohttps://doi.org/10.1080/00207721.2013.822124Published online:07 January 2015Display full size K. Krishna ChaitanyaK. Krishna Chaitanya completed his master's degree in Process Control and Instrumentation from Department of Chemical Engineering at National Institute of Technology, Tiruchirappalli, India. He is currently working for GE Oil & Gas, Hyderabad, India. His research interests include control systems and time delay systems. Improved PID controller design for unstable time delay processes based on direct synthesis method and maximum sensitivityAll authorsB. Vanavil, K. Krishna Chaitanya & A. Seshagiri Raohttps://doi.org/10.1080/00207721.2013.822124Published online:07 January 2015Display full size A. Seshagiri RaoA. Seshagiri Rao obtained his bachelor's degree in Chemical Engineering from Jawaharlal Nehru Technological University, Hyderabad, India. He obtained his master's degree from Indian Institute of Technology, Banaras Hindu University, Varanasi, India, in 2003 and PhD from Department of Chemical Engineering, IIT Madras, India, in 2007. After that, he joined NIT Tiruchirappalli in the Department of Chemical Engineering as an assistant professor. He published a book chapter in the book PID control in the third millennium: lessons learned and new approaches, Springer, 22 papers in referred international journals and 21 conference proceedings. His research interests include process control, time delay systems, multivariable control, nonlinear dynamics, process design and optimisation with application to waste water treatment plants and particulate processes. He has several masters and PhD students working with him on various projects. Improved PID controller design for unstable time delay processes based on direct synthesis method and maximum sensitivityAll authorsB. Vanavil, K. Krishna Chaitanya & A. Seshagiri Raohttps://doi.org/10.1080/00207721.2013.822124Published online:07 January 2015Display full size
Publication Year: 2013
Publication Date: 2013-08-20
Language: en
Type: article
Indexed In: ['crossref']
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