Title: Architecture of a high-rate VLSI Viterbi decoder
Abstract:The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis decoding. Although conventional Viterbi de...The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis decoding. Although conventional Viterbi decoders process all states concurrently, the sequential nature of this algorithm limits the decoding throughput for a given integrated circuit technology and thereby restricts its applications. This paper presents the architecture of a single-chip Viterbi decoder combining two methods to speed-up the data rate: the "radix" trellis method and the interleaved method. The resulting architecture is very attractive for applications where high-speed decoding is essential, such as satellite digital communication systems.Read More
Publication Year: 2002
Publication Date: 2002-12-24
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 7
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