Title: 200 kS/s, 10-Bit Low Power SAR ADC for Biomedical Applications
Abstract: In this paper, an Ultra-low power 10-bit 200kS/s Successive Approximation Register (SAR) Analog-to-Digital converter is presented. A Split-array charge distribution capacitive DAC is proposed. Spectre simulation results of single-ended 10-bit 200kS/s for supply voltage 1. 8V SAR-ADC in a 0. 18μm CMOS technology employing the proposed architecture show that the SAR ADC consumes 1. 502uW and ADC achieves SNDR of 57. 4dB. The ENOB 9. 24 resulting in a figure of merit (FOM) of 160fJ/conversion-step. Refer ences
Publication Year: 2014
Publication Date: 2014-10-29
Language: en
Type: article
Access and Citation
Cited By Count: 2
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot