Title: M*N Booth encoded multiplier generator using optimized Wallace trees
Abstract: The architecture and the design method for an M-*-N Booth-encoded parallel-multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is presented and explained. The final stage of adding two (N+M-1)-bit numbers is done by an optimal carry-select adder stage. An algorithm for optimal partitioning of the (N+M-1)-bit adder is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Publication Year: 2003
Publication Date: 2003-01-02
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 12
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot