Title: A high speed self-biased CMOS amplifier IP core
Abstract: A novel high speed 0.25 /spl mu/m CMOS amplifier IP core is presented which use the complementary self-biasing differential amplifier technique. The proposed amplifier features a 418 MHz unity gain frequency and 375 V//spl mu/s slew rate with capacitive load 2pF. The output voltage of the proposed amplifier swings from Vgnd to Vdd and the static power less than 0.32 /spl mu/W. A Verilog-A behavioral model is presented for the amplifier IP core which contains the important non-idealities of the amplifier.
Publication Year: 2005
Publication Date: 2005-09-09
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 2
AI Researcher Chatbot
Get quick answers to your questions about the article from our AI researcher chatbot