Title: Estimation and optimization of delay in popular CMOS logic styles
Abstract: This paper presents a unified model for delay estimation in various CMOS logic styles. It also derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area.
Publication Year: 2001
Publication Date: 2001-01-01
Language: en
Type: article
Indexed In: ['crossref']
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