Title: A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath
Abstract: In this paper, a cost-effective 2D discrete cosine transform processor using a reconfigurable datapath is described. The proposed architecture uses some multiplexers to reduce computational complexity. This processor operates on 8/spl times/8 blocks. Unlike other direct methods, the proposed architecture is regular for VLSI implementation. The proposed 2D DCT processor costs 38598 transistors, with an operating frequency of 100 MHz, using 0.35 /spl mu/m CMOS technology.
Publication Year: 2003
Publication Date: 2003-10-15
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 5
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