Title: ASIC Implementation of Reed-Solomon Error Correction Circuits for Low Area Overhead on Memory System
Abstract:Error Correction Codes (ECC) are employed to protect memory systems from soft fault errors for mass data processing of portable devices and large-scale integration circuits. Information stored in memo...Error Correction Codes (ECC) are employed to protect memory systems from soft fault errors for mass data processing of portable devices and large-scale integration circuits. Information stored in memory devices is vulnerable to soft errors due to low voltage and power consumption. Error correction codes such as Reed Solomon (RS) codes and Hamming codes require excessive chip area overhead to the implementation of memory circuits. In this paper, RS codes are implemented to FPGA and ASIC chips with 0.35㎛ CMOS standard cell process. The investigation of (255, 247) RS encoders and decoders with Berlekamp-Massey algorithm reveals 3.24% of that parity/data bit rate and 1.8㎟ of chip size. RS code circuit saves area overhead over Hamming code’s.Read More
Publication Year: 2008
Publication Date: 2008-06-01
Language: en
Type: article
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Cited By Count: 12
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