Title: Design of low power UWB LNA for frequency 3.1–5 GHz in 0.18 μm CMOS technology
Abstract: This paper present 3.1-5 GHz low noise amplifier (LNA) for UWB receivers. In this proposed circuit, cascade and cascode topology with modified input matching are designed. Proposed LNA achieves a maximum gain 22.252 dB, a noise figure 0.921-1.646 dB with a wide input matching. The power consumption is low under a 1.6-V dc power supply. The proposed UWB LNA is implemented using 0.18 μm based CMOS technology under TSMC.
Publication Year: 2015
Publication Date: 2015-05-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 1
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