Title: Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications
Abstract: In this article, we have explored the impact of drain spacer length optimization in 3-Fin-Tri-gate structure and single-Fin Tri-gate structure for mid band 5G application. Tri-gate Fin-FETs at 14 nm technology node are the best candidates for 5G application. However, the driving capability of single-Fin device is very low thus it is desirable to use multi-Fin structure for relatively high frequency RF application. Although multi-Fin-FETs are prone to parasitic capacitances but show better performance in terms of transconductance $(g_{m})$ and cut-off frequency $(f_{T})$ as compared to single-Fin based Fin-FET. It has been observed that by increasing the drain spacer while keeping fin length constant, a sufficient increase in drain current in the single-Fin as well as in 3-Fin structure can be achieved. The Same variation shows a drastic improvement in 3-Fin structure in terms of parasitic capacitances, unlike the single-Fin structure. The improved drain current and reduced parasitics eventually result in a very high cut-off frequency of 479 GHz, which is 36% higher than the single-Fin structure. An extensive comparison with the state-of-the-art design shows an improvement of 25% in f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> .
Publication Year: 2022
Publication Date: 2022-02-01
Language: en
Type: article
Indexed In: ['crossref']
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Cited By Count: 7
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