Publication Information

{'id': 'https://openalex.org/W2765125811', 'doi': 'https://doi.org/10.1109/cicn.2016.61', 'title': 'Design of a High Linear Integrator for Oversampled ADC', 'display_name': 'Design of a High Linear Integrator for Oversampled ADC', 'publication_year': 2016, 'publication_date': '2016-12-01', 'ids': {'openalex': 'https://openalex.org/W2765125811', 'doi': 'https://doi.org/10.1109/cicn.2016.61', 'mag': '2765125811'}, 'language': 'en', 'primary_location': {'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/cicn.2016.61', 'pdf_url': None, 'source': None, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}, 'type': 'article', 'type_crossref': 'proceedings-article', 'indexed_in': ['crossref'], 'open_access': {'is_oa': False, 'oa_status': 'closed', 'oa_url': None, 'any_repository_has_fulltext': False}, 'authorships': [{'author_position': 'first', 'author': {'id': 'https://openalex.org/A5000974773', 'display_name': 'Varun Mishra', 'orcid': 'https://orcid.org/0000-0002-9264-9338'}, 'institutions': [], 'countries': ['IN'], 'is_corresponding': False, 'raw_author_name': 'Varun Mishra', 'raw_affiliation_strings': ['VLSI Design Faculty of Technology, UTU, Dehradun, India'], 'affiliations': [{'raw_affiliation_string': 'VLSI Design Faculty of Technology, UTU, Dehradun, India', 'institution_ids': []}]}, {'author_position': 'middle', 'author': {'id': 'https://openalex.org/A5036155778', 'display_name': 'Abhishek Bora', 'orcid': None}, 'institutions': [], 'countries': ['IN'], 'is_corresponding': False, 'raw_author_name': 'Abhishek Bora', 'raw_affiliation_strings': ['VLSI Design Faculty of Technology, Dehradun, India'], 'affiliations': [{'raw_affiliation_string': 'VLSI Design Faculty of Technology, Dehradun, India', 'institution_ids': []}]}, {'author_position': 'last', 'author': {'id': 'https://openalex.org/A5065036562', 'display_name': 'Vishal Ramola', 'orcid': None}, 'institutions': [], 'countries': ['IN'], 'is_corresponding': False, 'raw_author_name': 'Vishal Ramola', 'raw_affiliation_strings': ['VLSI Design Faculty of Technology, Dehradun, India'], 'affiliations': [{'raw_affiliation_string': 'VLSI Design Faculty of Technology, Dehradun, India', 'institution_ids': []}]}], 'institution_assertions': [], 'countries_distinct_count': 1, 'institutions_distinct_count': 0, 'corresponding_author_ids': [], 'corresponding_institution_ids': [], 'apc_list': None, 'apc_paid': None, 'fwci': 0.0, 'has_fulltext': True, 'fulltext_origin': 'ngrams', 'cited_by_count': 0, 'citation_normalized_percentile': {'value': 0.0, 'is_in_top_1_percent': False, 'is_in_top_10_percent': False}, 'cited_by_percentile_year': {'min': 0, 'max': 66}, 'biblio': {'volume': None, 'issue': None, 'first_page': None, 'last_page': None}, 'is_retracted': False, 'is_paratext': False, 'primary_topic': {'id': 'https://openalex.org/T10323', 'display_name': 'Analog Circuit Design for Biomedical Applications', 'score': 0.9994, 'subfield': {'id': 'https://openalex.org/subfields/2204', 'display_name': 'Biomedical Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, 'topics': [{'id': 'https://openalex.org/T10323', 'display_name': 'Analog Circuit Design for Biomedical Applications', 'score': 0.9994, 'subfield': {'id': 'https://openalex.org/subfields/2204', 'display_name': 'Biomedical Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T11992', 'display_name': 'CMOS Image Sensor Technology', 'score': 0.9839, 'subfield': {'id': 'https://openalex.org/subfields/2208', 'display_name': 'Electrical and Electronic Engineering'}, 'field': {'id': 'https://openalex.org/fields/22', 'display_name': 'Engineering'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}, {'id': 'https://openalex.org/T12564', 'display_name': 'Networked Smart Transducer Interface Standard', 'score': 0.9762, 'subfield': {'id': 'https://openalex.org/subfields/1705', 'display_name': 'Computer Networks and Communications'}, 'field': {'id': 'https://openalex.org/fields/17', 'display_name': 'Computer Science'}, 'domain': {'id': 'https://openalex.org/domains/3', 'display_name': 'Physical Sciences'}}], 'keywords': [{'id': 'https://openalex.org/keywords/linearity', 'display_name': 'Linearity', 'score': 0.8589276}, {'id': 'https://openalex.org/keywords/integrating-adc', 'display_name': 'Integrating ADC', 'score': 0.63058585}, {'id': 'https://openalex.org/keywords/pixel-level-adc', 'display_name': 'Pixel-Level ADC', 'score': 0.508617}, {'id': 'https://openalex.org/keywords/delta-sigma-modulation', 'display_name': 'Delta-sigma modulation', 'score': 0.4856035}, {'id': 'https://openalex.org/keywords/passive-integrator-circuit', 'display_name': 'Passive integrator circuit', 'score': 0.48082983}], 'concepts': [{'id': 'https://openalex.org/C79518650', 'wikidata': 'https://www.wikidata.org/wiki/Q2081431', 'display_name': 'Integrator', 'level': 3, 'score': 0.92869675}, {'id': 'https://openalex.org/C77170095', 'wikidata': 'https://www.wikidata.org/wiki/Q1753188', 'display_name': 'Linearity', 'level': 2, 'score': 0.8589276}, {'id': 'https://openalex.org/C155745195', 'wikidata': 'https://www.wikidata.org/wiki/Q1164179', 'display_name': 'Comparator', 'level': 3, 'score': 0.72262836}, {'id': 'https://openalex.org/C140020054', 'wikidata': 'https://www.wikidata.org/wiki/Q6043185', 'display_name': 'Integrating ADC', 'level': 5, 'score': 0.63058585}, {'id': 'https://openalex.org/C81299745', 'wikidata': 'https://www.wikidata.org/wiki/Q334269', 'display_name': 'Transfer function', 'level': 2, 'score': 0.568322}, {'id': 'https://openalex.org/C24326235', 'wikidata': 'https://www.wikidata.org/wiki/Q126095', 'display_name': 'Electronic engineering', 'level': 1, 'score': 0.534902}, {'id': 'https://openalex.org/C41008148', 'wikidata': 'https://www.wikidata.org/wiki/Q21198', 'display_name': 'Computer science', 'level': 0, 'score': 0.5270914}, {'id': 'https://openalex.org/C65655974', 'wikidata': 'https://www.wikidata.org/wiki/Q14867674', 'display_name': 'Swing', 'level': 2, 'score': 0.5177126}, {'id': 'https://openalex.org/C46362747', 'wikidata': 'https://www.wikidata.org/wiki/Q173431', 'display_name': 'CMOS', 'level': 2, 'score': 0.5015826}, {'id': 'https://openalex.org/C131021393', 'wikidata': 'https://www.wikidata.org/wiki/Q7512759', 'display_name': 'Signal transfer function', 'level': 4, 'score': 0.49869895}, {'id': 'https://openalex.org/C68754193', 'wikidata': 'https://www.wikidata.org/wiki/Q1184820', 'display_name': 'Delta-sigma modulation', 'level': 3, 'score': 0.4856035}, {'id': 'https://openalex.org/C30839866', 'wikidata': 'https://www.wikidata.org/wiki/Q918242', 'display_name': 'Passive integrator circuit', 'level': 5, 'score': 0.48082983}, {'id': 'https://openalex.org/C47446073', 'wikidata': 'https://www.wikidata.org/wiki/Q5165890', 'display_name': 'Control theory (sociology)', 'level': 3, 'score': 0.47779116}, {'id': 'https://openalex.org/C184720557', 'wikidata': 'https://www.wikidata.org/wiki/Q7825049', 'display_name': 'Topology (electrical circuits)', 'level': 2, 'score': 0.44440395}, {'id': 'https://openalex.org/C2780023022', 'wikidata': 'https://www.wikidata.org/wiki/Q1338171', 'display_name': 'Compensation (psychology)', 'level': 2, 'score': 0.44111574}, {'id': 'https://openalex.org/C52192207', 'wikidata': 'https://www.wikidata.org/wiki/Q5322', 'display_name': 'Capacitor', 'level': 3, 'score': 0.25737464}, {'id': 'https://openalex.org/C127413603', 'wikidata': 'https://www.wikidata.org/wiki/Q11023', 'display_name': 'Engineering', 'level': 0, 'score': 0.22937456}, {'id': 'https://openalex.org/C119599485', 'wikidata': 'https://www.wikidata.org/wiki/Q43035', 'display_name': 'Electrical engineering', 'level': 1, 'score': 0.16980347}, {'id': 'https://openalex.org/C13412647', 'wikidata': 'https://www.wikidata.org/wiki/Q174948', 'display_name': 'Analog signal', 'level': 3, 'score': 0.16134131}, {'id': 'https://openalex.org/C2776257435', 'wikidata': 'https://www.wikidata.org/wiki/Q1576430', 'display_name': 'Bandwidth (computing)', 'level': 2, 'score': 0.14034414}, {'id': 'https://openalex.org/C39394816', 'wikidata': 'https://www.wikidata.org/wiki/Q939318', 'display_name': 'RC circuit', 'level': 4, 'score': 0.13804898}, {'id': 'https://openalex.org/C84462506', 'wikidata': 'https://www.wikidata.org/wiki/Q173142', 'display_name': 'Digital signal processing', 'level': 2, 'score': 0.07857132}, {'id': 'https://openalex.org/C76155785', 'wikidata': 'https://www.wikidata.org/wiki/Q418', 'display_name': 'Telecommunications', 'level': 1, 'score': 0.07564464}, {'id': 'https://openalex.org/C165801399', 'wikidata': 'https://www.wikidata.org/wiki/Q25428', 'display_name': 'Voltage', 'level': 2, 'score': 0.07238817}, {'id': 'https://openalex.org/C78519656', 'wikidata': 'https://www.wikidata.org/wiki/Q101333', 'display_name': 'Mechanical engineering', 'level': 1, 'score': 0.0}, {'id': 'https://openalex.org/C15744967', 'wikidata': 'https://www.wikidata.org/wiki/Q9418', 'display_name': 'Psychology', 'level': 0, 'score': 0.0}, {'id': 'https://openalex.org/C2775924081', 'wikidata': 'https://www.wikidata.org/wiki/Q55608371', 'display_name': 'Control (management)', 'level': 2, 'score': 0.0}, {'id': 'https://openalex.org/C154945302', 'wikidata': 'https://www.wikidata.org/wiki/Q11660', 'display_name': 'Artificial intelligence', 'level': 1, 'score': 0.0}, {'id': 'https://openalex.org/C100329506', 'wikidata': 'https://www.wikidata.org/wiki/Q336439', 'display_name': 'Ćuk converter', 'level': 4, 'score': 0.0}, {'id': 'https://openalex.org/C11171543', 'wikidata': 'https://www.wikidata.org/wiki/Q41630', 'display_name': 'Psychoanalysis', 'level': 1, 'score': 0.0}], 'mesh': [], 'locations_count': 1, 'locations': [{'is_oa': False, 'landing_page_url': 'https://doi.org/10.1109/cicn.2016.61', 'pdf_url': None, 'source': None, 'license': None, 'license_id': None, 'version': None, 'is_accepted': False, 'is_published': False}], 'best_oa_location': None, 'sustainable_development_goals': [], 'grants': [], 'datasets': [], 'versions': [], 'referenced_works_count': 5, 'referenced_works': ['https://openalex.org/W1501298798', 'https://openalex.org/W1988727019', 'https://openalex.org/W2058682135', 'https://openalex.org/W2096567638', 'https://openalex.org/W4214744378'], 'related_works': ['https://openalex.org/W4385656577', 'https://openalex.org/W326711262', 'https://openalex.org/W2765125811', 'https://openalex.org/W2517094076', 'https://openalex.org/W2388167301', 'https://openalex.org/W2352536396', 'https://openalex.org/W2143449266', 'https://openalex.org/W2090668620', 'https://openalex.org/W2058962136', 'https://openalex.org/W2032779953'], 'abstract_inverted_index': {'This': [0], 'paper': [1], 'represents': [2], 'a': [3], 'method': [4], 'to': [5, 43, 60, 85], 'enhance': [6], 'the': [7, 36, 44, 53, 78, 107], 'linearity': [8], 'of': [9, 26, 46, 52], 'an': [10, 47, 71], 'integrator': [11, 66], 'by': [12, 98], 'implementing': [13], 'feedback': [14, 32], 'compensation': [15], 'topology.': [16], 'The': [17, 64, 80], 'proposed': [18, 65], 'design': [19, 67, 83, 95], 'reduces': [20], 'signal': [21, 37], 'swing': [22, 56], 'while': [23], 'keeping': [24], 'advantages': [25], 'both': [27], 'feed-forward': [28], 'as': [29, 31], 'well': [30], 'topology': [33], 'without': [34], 'changing': [35], 'transfer': [38], 'function.': [39], 'Linearity': [40], 'is': [41, 58, 96], 'related': [42], 'output': [45, 55], 'integrator.': [48], 'Non-linearity': [49], 'resulted': [50], 'because': [51], "integrator's": [54], 'that': [57, 105], 'due': [59], 'change': [61], 'in': [62], 'input.': [63], 'when': [68], 'integrated': [69], 'with': [70], 'oversampled': [72], 'ADC': [73], '(ΣΔ': [74], 'ADC)': [75], 'significantly': [76], 'increases': [77], 'linearity.': [79], 'latch': [81], 'comparator': [82], 'used': [84], 'implement': [86], 'first': [87], 'order': [88], 'sigma-delta': [89], 'modulators': [90], 'also': [91], 'discussed.': [92], 'All': [93], 'discussed': [94], 'implemented': [97], 'using': [99], '180nm': [100], 'CMOS': [101], 'technology': [102], 'and': [103], 'simulation': [104], 'verifies': [106], 'results': [108], 'are': [109], 'given.': [110]}, 'cited_by_api_url': 'https://api.openalex.org/works?filter=cites:W2765125811', 'counts_by_year': [], 'updated_date': '2024-09-26T15:53:56.155737', 'created_date': '2017-11-10'}