Title: Design and Implement an IP-Core for Multiplex Data Bus 1553B
Abstract: Architecture, implementation and fault tolerant design method of a proprietary intellectual property (IP) core for implementing MIL-STD-1553B protocol on field programmable devices is discussed. The IP core was coded with Verilog hardwre description language. It can be implemented on any field programmable device containing more than 100,000 equivalent gates. Previous research works are usually based on embedded processor or digital signal processor (DSP) with their bus interface chips performing tasks on data link layer. Different from those previous work, the proposed IP core can automatically accomplish tasks on data link layer and transport layer after initiation. In addition, it has a bulid-in self testing feature. In experiment, the IP core replaced the chip UT1553B BCRTM made by Aeroflex/UTMC without modifying any other hardware or software. The experiment results show that the system perform well and can accord with the protocol.
Publication Year: 2007
Publication Date: 2007-01-01
Language: en
Type: article
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