Title: A SW-HW implementation of arbitration protocols
Abstract: In this study, we discuss arbitration aspects concerning a segmented bus platform for SOC, and analyze a software implementation of the related procedures. Placed somewhere mid-way between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology.
Publication Year: 2005
Publication Date: 2005-04-25
Language: en
Type: article
Indexed In: ['crossref']
Access and Citation
Cited By Count: 3
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